Is there any standard for pin number? No. You can use whatever you want. You can use a query pin or a for pain. The choice is yours angles. Does that answer your question? Yes. Awesome. Ask question and our swatch now, if there is any standard for the older like to first being is for policies and the second is 4 negative and Australia, so Guang I adjust the sign. No, that's not really what is the practise is to the positive terminal and a negative end underground in the middle. Okay. Just does just what it is. Okay. Yeah. That's fine. Okay. So you work on so as I've mentioned, do the recording has started that in today's lecture we're going to talk about Sallen-Key define the lithium been that our sense of observation I've observed in some of your designs while Mackenzie schematic, that I think we need to go over Sallen-Key once again. And also discussions on the discussion board indicated something about candy cutoff frequency of the Sallen-Key. Be different when you do it by copulation and when you simulate the circuit itself, or can they be DC? Of course you debit it. We want to go over that a little bit and we then talk about the requirement for your final report toward them. So I'm going to start now by presenting a few slides. So this is week 8, and we shall be talking about Sallen-Key designed very briefly. So what we'll be looking at in this session is about the cutoff frequency you obtain from the calculation and that which you obtain when you simulate your system in LTSpice. The requirement is for a fourth order Sallen-Key low-pass philtre. But you can get the fourth order by cascading two double pole. Alright, therefore, I'm going to consider just a two-port Sallen-Key low-pass philtre here with the assumption that you can combine two or base to get your four poor Sallen-Key. For defining key configuration, the cutoff frequency is given by the equation here, which we're all familiar with. And again is ratio of R2 to R1 plus 1. That is the gain of this. What is not shown here is another parameter that is the decay factor, obviously sign. The Q factor tells us our flak. The response is going to be an almost peaking that you get in your Bode plots. I'm sure we're all familiar with that concept now, what that Q factor is equally important. We'll talk a bit more about it clearly lit well. Therefore, when you're designing your Sallen-Key philtre, you need to consider the Q factor. Your design, you need to decide on your cutoff frequency. If you decide on your EFC, then from this expression here, you can work out the values of our three or four. I'm C1 and C2. You can decide to simplify this cut-off frequency equation by making L3 equals to R4 and by making c1 equals to C2. If we do that, then the equation reduces To, let me see if I can get the pain. So the equation reduces to one over two pi r, c we are, is now R3 because of our four, and C is now C1, C2. You don't have to do that. But if an option to simplify the design process, you can find a lot more information on the additional material that I put on Learn on foreign key design. Once you've done definitely vacation, then you can now decide to choose the values of your C and D. One of our whatnot that the input capacitance of your op-amp is important and might affect the response that you get. Therefore, it will be better to measure that in this controversially as seen here, the input capacitance is not shown. Both is going to be somewhere here. In the input terminal. There will be a capacitance here that the input is something that we do not see, but it's present in the op-amp. Op-amp has it input capacitor and it will be connected to ground as well. Okay? So this one is seen, which is the input capacitance of the op-amp. So what we want to happen is that C1 should be bigger than c. In that is when this equation, we be getting something close to what you expect, that is when the sequencer will make sense. If you're C1 is at least Brieger or maybe uplift the same value or bigger than c. If c in apples to dominate if c is bigger, then what you get from this equation is not going to be accurate when you carry out your simulations. Because you have a defined capacitance taking hold in your design. I will do some simulation example, Lee Twan, to clarify those points. One child legged do is that we don't always know develop OBC in a times the manufacturer of the opamp my specified that value in the data sheet. But in most cases they don't. So we really don't know. But from practise, we do know that input ka, ka is typically around ten Pico, maybe a bit more, maybe a bit less, depending on the op amp up around that ballpark figure. 10 picofarad does a ballpark figure for the input capacitor. That's fine for simulation. But if you were to build this design in the lab, there's something else to worry about. And that is the stray capacitance that is carpus back that confirm a time for the environment, a time from the board itself. Got you really cannot quantify. As an example, where you put a resistor on the board, particularly a through hole. We see. So he asked two pins, those two pins deform a capacitor because the capacitor is to pile up, is with a dielectric in the middle. So different. You have to pay me Sister forms a capacitor, and that is an example of a stray capacitance. C1 asked to terminus as well. The two conductors damage the terminus of C1, deform stray capacitance. So also all disorderly system. So they add up to district CA, quantity bought. So that is why when you build the circuit in the lab, even if your calculation agrees with your simulation, where you build is going to be different because of this stray capacitance effect. Okay? Unfortunately, we cannot demonstrate that in this course because we're not building a saccades and discuss both, we can look at effect of the input capacitance. So if you choose your component values very carefully, then the cutoff frequency from stimulation and from calculation will be identical. If we take the points I mentioned earlier into account. In other words, the CE. If you're very careful, then you can make your simulator and the Capulet family been quite close. Again, I repeat it. Input capacitance dominates the you, my archives in your simulation results. The capacitance, as we said, the input once about 10 people. So we want to avoid C1 bill less than 10 picofarad because our cost tabu. So your choice of c1 xi be no less than 10 picofarad to avoid all of these issues. That's point number one. Point number two is, while you do all of that, is you also be cognisant of the gain bandwidth limitation. As a rule of thumb, as a guide, the guide, your expected gain multiplied by your expected cutoff frequency should be far, far greater than the gain bandwidth product of your op-amp. Indicate than your pump it that apples to be decayed, then your op-amp will be able to meet the requirement or meet the demand you are placing on it. Note the entire relationship between Q factor and cutoff frequency. As an illustration, I'll make a quick sketch here. Or if I can sketch the Bode plots like that. So this is a sketch of a Bode plot. If you're a Q factor is less than one, you might guess something. This nice. New HomePod, I slow oscillation. There's no peaking. It's nice and flat. Ignore this horizontal line here. So this is your Bode plot with no picking. But if he have Q factor that is quite big, like one and above, we might start to have this hump here. Is the coal mine I'm drying ongoing. So these with the home, we affect your cutoff frequency because how do you measure the cutoff frequency issue be fully dB below the maximum value. So do you measure with respect to the flat region or do you measure it with respect to the peak value here? If you have this hump day. So that causes a lot of complications. And that's what this last point is in phi into desk a kind of interrelationship between Q factor and the cutoff frequency. Do we have any questions of ice? The point I'm getting across clear to everybody at the state before we continue. Yep. Is the point I'm trying to get across clear about the compromise that we need to make when it comes to Sallen-Key design. Okay. I can't hear anything back from anybody, so I assume that is a yes. So to illustrate basic command line seeing what that is. Yes, thank you. Thermos. So to illustrate all of that a lot more, we need to do some simulation using LTSpice and compare with what the cartilage on stays. So I've got a number of case studies. The first one I'm going to look at is for simplicity, I'm making in this equation here, in this design, I'm making my R3 to be cause for, and I'm making my C1 to C2. So I simplify my cutoff frequency to be 1 divided by 2 pi over RC. Okay, so because I'm making a simplification, so that means my equation is not a lot easier to pi over two pi RC. And also I big, I want equals to out to you here. R1 equals R2, then the gain becomes two. And that's what I'll put it. That is my I thought it don't. After you do that, I'm doing that for simplicity for the sake of this presentation. So it is IGF numbers that are plucked from the a, just a random number. Say let my receipts or be 10 K by capacitance will be 10 picofarad. We said it should not be less than 10 people. 10 people. If you put these two numbers into the design equation, you get fc calculate at any 1.6 megahertz. Now we want to try and simulate this and see what we get. So I go into LTSpice. I believe my screen is sharing. If you cannot see my LTSpice, then please let me know. Very chatbox. So my add one, I said I want this to be 10 K on my arm to the same value, 10 kiloohms. And I want the capacitors to be ten Pico. I think that is just to be sure, yes, ten Pico as well. For the capacitors, I want them to be 10 pico. So 10 picofarad and T1 here. Before it. The calculation said the bandwidth, the cutoff frequency of about 1.6. So we do the simulation. We measure are the outputs here and as the blue curve, so it's nice and flat. The maximum value is about negative 710 power. Okay, sorry, it has a mistake. In UC Davis Sr. they are not the same upset. I want them to be the same. So let me change this wants to 550. 550, so that again is to 550. So our three equals to R4 because of 550 docx file to do my simulation again. And this, so if I look at the flat region, D gate is about negative 13.9 as three dB, that becomes negative 16.9. So does just on the negative seventh in, if I do that, somebody around here, somewhere around here does this, what should be, and that is giving me about 1.85 megahertz. So I've done the simulation and is giving me 1.85, but the calculations, this tissue Give me 1.6. So outtake that, that is close enough time. So in that case, I will say my calculation and the simulated, the ADD the cutoff frequency from simulation. They are in agreement because they are close enough. Is that clear to everybody? What I've done here, so that's fine. What I want to do next is to now consider a different scenario. One I call case to. In my case 2. If I reduce my oldest sister by a factor of 10, and I keep the value of my C. Remember, the cutoff frequency is given by one over two pi RC. If you reduce actually by a factor of 10, that the cut-off frequency as the go up by the same factor. So reducing my r to one kilo from ten, She gave me a cutoff frequency of 16 megahertz for my calculation. What I want to do is do that in LTSpice and see what I get for my simulation. So I go back to my LTSpice and I change my resistor 2 1 kilo ohm, one kiloohm, and I leave the capacitor as they are. One kiloohm and 1D simulation. Then I look at the flat region. I've got negative 30, 97, about negative 14, 3 dB below that, close to negative 17. But just on the and that should be somewhere around here. So I got 16.69, the calculation and safest GB 16. And I go 16 points, 69. Again, that is close enough. I'm happy with that. So I will say the calculated value on data obtained from simulation are close enough, so no problems at all. I go to case 3. Let's now see what happens if you keep the cup to be 10 kiloohm, but reduce the capacitor by a factor of 10. Efc calculator should still remain 60 megahertz. But do note that this is now below ten Pico, potentially below the input capacitance of my op-amp. Let's see what happens when we do the simulation for this new value. So C has changed to one picofarad. Why R is now 10 kiloohm. So r is 10 and C is one pico. Pico. And then I do the simulation again. Right? So if we look at this in the flat kitchen, is still 14 minus 17 is a three dB point, but sin is about 6.9 megahertz fixed point night, we are expecting 16, but I guess it's 0.9. Therefore, that will not work. Okay. So he did not walk in that case because the capacitance value is below the input capacitance of the op-amp. So a breakdown, we get there. So that is case three, that is an illustration of not using death. An illustration of the effect of the small c. I go to 100 I want. Let's look at the effect of gain bandwidth product with respect to case one. Finally, this my by a factor of 100. So if I reduce by factor of a 100, that means the bandwidth goes up by a factor of 100. So the bandwidth, she become 160 megahertz. Polybase. I'm using a legacy 14. That op-amp gain bandwidth product is 100 megahertz. So I don't have enough to achieve 160. It's just not enough time. So let's see what happens if you try to do that for my simulation is going to be erroneous, we know that, but let's just demonstrate. So that is one hundred and twenty one hundred and ten picofarad. So 2110000010 people. Okay, So I've got that. And then I do the simulation at the output here. So from here we see the gain is still about negative 14, 3 dB below that is somewhere around here, about 80. So about it because the op-amp cannot give us 16. And that is to demonstrate the limitation caused by gain bandwidth product. Do we have any questions so far? Author? I wonder whether it also makes effect. If I decide if the capacitance is to let, we shall get to that in a minute. Neuroscience. So you should make your capacitance to big Edward. You said, I think tau, okay, you are responding to Arthur. He said, that will make your thoughts Exactly. So if you make a Pascal is too big, you know, reciprocal. So if you increase capacitance, you have to reduce your system to keep the cutoff frequency and vice versa. So if you want, if your capacitor is too big, you only start becomes too tiny that you also run into trouble. All right, so that's, that's, that's a very good point. And also look at this couple. So C2, it is that the output of an op-amp. So if it becomes too big, he also wanting to toggle because op-amps don't like to drive capacitive load time, so we cannot just increase it arbitrarily. We have to be very cautious. So I look at another case, five, which is the effect of C and Q factor. Now, I just want to try out to be 100 and C to be 220. Now my c is big. In response to your question. Before ours you see a maximum of ten pico. Now I want to use 220, quite a big value, but I reduce my sister to 100. If you plug these two numbers in, the EFC calculated is 7.2 megahertz. Let's try the simulation and see what we get. 100 and 220. So one hundred and twenty, one hundred and twenty two twenty here. And simulate. So I've done my simulation now. And that gives me, at here, you can see the Q factor is no longer very smooth and flat. I have this little hump around the cutoff frequency here. And that is because my Q factor for this design is one, is not less than one. That's why you have to opt in, but that's not too bad. So I'm using two, so that's about negative 14. And I go up until negative 17. I think GDB episodes in here. So give me something like 8.76487777. I was expecting point to give me a 0.77. I'll take that as close enough. But, but I have this Q factor issue. Instead of measuring with respect to D flat Gaddafi by the maximum gain. If I measure with respiratory maximum value here. So the maximum value is negative 12 dB, three dB below that takes me to the negative 15, somewhere around here. And that is 7.8. That is much more closer to what I was expecting 7.2 simulations and pointed. Say that it's close enough, so I'm happy with that. But that is illustrating the interplay between a, B, C and D Q factor. I hope that is clear to everybody. I'm happy to take questions at this point. So this is the approach that we can take to make sure that the calculation and the simulation, they are in agreement. I'm happy to take questions at this point. If there are any any questions before we continue or comments or observations. Is the message I'm trying to pass across clear to everyone? Edward. Is that clear? I know you responded. Yeah. Yes. Hello? Yes. So in one of the documents provided, there was a suggestion that the capacitors should not be smaller than a 100 picofarads. Is that also with keeping? Is that also with regards to trying to make sure that the input capacitance does not really have an effect. Exactly. So on the apical fired is a good suggestion if you want to build is. Remember at the beginning I mentioned something like input capacitance as well as the stray capacitance. Especially in the simulation. I'm not taking three capacitors into account, but if we are building in the lab, in addition to see in, you have to account for stray capacitance. District capacitance is very difficult to quantify. Therefore, the suggestion from experience, from practise of using a capacitor that is no less than 100 picofarad. If you were to build this in the lab and you realise I see. I understand. Thank you. You're welcome. Anymore questions? Hopper okay. Or toys clay now. So if that is clear, then we can move on. Unless there are any other questions or comments from anyone. Yes, go on here. Very quick, very quick question. So we should also consider the Q factors when we decide that and key. Yes. That's what I've been saying all along. Because the Q factor will determine our blood. Your response is yes, an MVC. And I see in the materials it says, uh, for, for all does the encase the first stage at our 0.5 and at a second stage are better at one country. Our Cleopatra as their eyes. What did you read from the material if I put it back to you, it depends on what kind of philtre you want to design. Remember, you cannot Buddha what philtre? You can Chebyshev, You can have elliptical, the unassigned. So for example, booth I watch philtre DIC is maximally flat, so the Q factor for that is 0.707, that is when is maximally flat. So if you concatenate two stages together. You said one is 4.5, roughly that I want. It's about 1.4. Lawfully, when you multiply them together, you get 2.7 and that gives you a response if that's what you're after. How? So? If Q factor is super power, artefacts is smooth, there's no line. I'm not sure I got your comments. Can you say that again if you don't mind. Yeah. I mean, if the Q factor is still 20 yeah. The FECA far for the Panther ways artist, as someone is at at a. At a. Let's begin. Yes. So the Q factor you choose will determine the kind of or against policy are going to get. I just give one example of put I would put out as Q factor of 0.707 EP designed to philtre correctly, then the response is going to be flat. You wouldn't have any you wouldn't have any. Hope you wouldn't see it at all? Yeah, it'll be very smooth. And I bought this amount of home, right? Not bad, not bad at all. The hump you get there can come from or that force this. You can confirm your TIE. You understand it's not decided keys, foreign keys, not the only subsystem that can cause these are piquing your TA can also cause picking. So just bear that in mind, okay? Okay. Okay. Thank you very much. Excellent. So next question, Edward. Yes, I do you want to ask your question directly, joseph? We've got about two minutes to do that. Yeah. I'm just wondering about the eye icon is designed. My circuit was mainly the final output of mine. So just anarchy filler does have a slight hump, however, the final output doesn't. So is that okay? That's fine. That's fine. Remember just to, in a way of bringing the comments from the last student, which was that you can have two stages. Once that as a Q factor of 0.5, do I don't want assay keep out of 1 something, 1.4 or something, right? So do you want to add 1.4? We have a hump in it for that home. Combined with the previous stage mixture that the output without being smooth? I don't know if that makes sense. Uh-huh. So in your case, yes, you might have a little hump in one of the intermediate stages, but overall, everything is nice and smooth. That's fine. It's like if you work on Edward quickly. Yes. It was just to clarify, if there is if there is a hump, we can choose to calculate f c as the minus three dB frequency from the top of the hump instead up the flatband? Yes, if you want to be sure whether your simulation is doing what you've calculated. Okay, my club, we show that is fine. Because the reason why I'm not going to suggest that all of the time is that it's possible your design is not right. That is passed to oscillate and this hump gets very big, like four dB, five dB, db. In that case, you have to look at, again because it's oscillating, Thomas is not stable. So if that happens that your home is more than three dB, my suggestion is to input a fine grit due to transient analysis. Input a sine wave in time domain and look at the output idea, identical. I see the yellow tends to say, Yes, I understand. It's stable. The hump will be smaller. So we can do actually is to take the three tp pick recall it from the top of the hump? Correct. Okay. I understand. And that will confirm that. I agree. Which a calculation? Yeah. Yeah. Excellent. So let's move on. So that is that about Sallen-Key design and all of the factors to consider. So the next thing I want to talk about is your final report. The information I'm presenting here, you find the same information in your course, Manuel, to take. So your final report should contain all the information, all technical information needed for someone else to produce new design independently. And now include the choice of components or the component values. Define our optimised schematic diagram. We did submit schematic in week four is possible that that has changed too. We want to see the very final one. We want to see define our PCB layout and is 3D representation if possible. That is important because the assumption is whatever you design will be sent away to a practise on way for it to be manufactured. So didn't need to have all the information. They need to build your socket. So that is the assumption here. We want to see the Catholics general result of your design. You said are built it, it should meet this specifications that is important for somebody that is going to replicate your board. So they can, you know, take the measurement and match it against what you have measured as the designer in this case. And who like to see the response to all the specific questions in the labs shadow. Once you kinda get sponsored. In terms of the marking criteria that is on page 9 of the course. So if I go to page nine and it's all day, I believe you can see. I'm trying to make it a bit bigger so we can all see, so we want it to be complete and your design must conform with the design specification. For example, define our cut-off frequency should be between 5.8 megahertz. It should be clear. You can add some originality to it. That choice is yours. Amen against the, against anything you have, and so on and so forth. So you can add more functionality to your design. Functionality in terms of where they can block any DC. Do we have any DC offset aref final outputs. How big is the peaking? If there's any, how stable is your design? How flat is it in the passband region? And what is this loop? In the I'm stopband region. We want to look at the quality of your PCB layout. This is so massive that laying the track is so easy. And everybody becomes too costly because it's too big. So we look at things like that. And then we want to look at your performance results. And finally, the structure of your report. There's no point in doing a design that you cannot present in a concise manner. So one of the learning objectives of this course is your ability to concisely report on what you've done. And that is what this report and we'll be examining. In addition to this marking criteria, we have the marking sheet or the feedback sheet, if you like. And that is on page 17? I believe. So. On page 7 seen I'm just trying to school day to P7 thing. So you see this, MacKenzie, this is what we use when marking. And it's good that you have visibility of what would be your 31st part. Asked three components to it. So that is the organisation of your report. What about his torso? I'm not going to be prescriptive on how you structure your APA because your designs are not the same. So use your own judgement to present your report in a very logical manner to what you are doing, and so on and so forth and your results and so on. And then we want to look at the editor ya quality. By that we mean things like we are typos Cordoba, the report is the report readable? Does it makes sense? When you read it? Can you understand what is within the and then completeness and conformity we design specifications have talked about that earlier. Part 2 will be your responds to task F, G, and H. Then remember, in those tasks, you've been asked to comment on some of your observations. So how well you respond to those questions will be assessed in part b. And in terms of Excellence Indicator, we're looking at a very well-structured report with clear appreciation of the overall objective of this exercise, we want to see a detailed and insightful interpretation of your results. If you're presenting results, you need to say something about it that I measured my cutoff to be five. Or worry about, you need to tell us what it is. What does that mean? And that's what we were referring today in some of the tasks, you've been specifically asked to comment. If you look at the task FG and each, you've been asked to comment on your observation. So we want to see your response to all of that. I'm trying to school there. Yeah, for example, in this task, here, it says comment on your observation that is comparing your theoretical bandwidth, which are measured bandwidth and you have been asked to come in. So we want to see your response to that kind of coming. And with that, I come to the end of my presentation for this session. So I'm open to questions and I'll do my best to answer your questions now. So thank you. Any questions? Yes questions. He has gone. Hello. Just a quick question. So I wanted to ask the structure of it. Pause is followed by the page 17. Organisation requires some sort of pop months and Apache sorry. We're in Part 1, we're going to be examining the structure of your report. Does the organisation does the structure? Does that answer your question? I saw so we can create structures by ourselves? Yes. Okay. Thanks. Another question. Douglas, do you want to ask your question? Yeah. I just fantastic. We should attach a table of the measurement scale. I think that's worth them manually stating and the ones used for their vote also all the peak-to-peak voltages and FeS is that included in the page count because it will take quite a lot of space. Exactly. So I will leave that to you, diagnose. So you look at the way if you read to you and if you think that information is valuable, then put it remember you can have appendix as well. I think let me see what's the Manuel says in terms of appendix. So it's an appendix included in the page count or it does what I want to double-check. I want adoption. But you can always puts extra information in the appendix. But your lab reports should be 10 pages maximum. But I will double-check on the append is and I will let you know. I'm trying to see if it says here where IT stupid. I know ambition to anything else? Yes. Well, it unless sure it is. Okay. That's fine. I'll double-check and I'll get back to you on that. Thank you. You're welcome. Anymore questions from anyone? I know I mentioned appendix in one of our double-check and and our client right up to that multipotent. Yes. Anymore questions or comments. So I'm going to stop recording right now. Okay.